RM0352 datasheet(121/138 Pages) STMICROELECTRONICS

121 / 138 page

DocID024647 Rev 1

121/138

RM0352

UART (universal asynchronous receive transmit)

137

12.6.2

Receive status register / error clear register, UARTRSR/UARTECR

The UARTRSR/UARTECR register is the receive status register/error clear register.

Receive status can also be read from the UARTRSR register. If the status is read from this

character read from the data register, UARTDR - see

Section 12.6.1 prior to reading the

UARTRSR register. The status information for overrun is set immediately when an overrun

condition occurs.

A write to the UARTECR register clears the framing, parity, break, and overrun errors. All

the bits are cleared to 0 on reset.

Table 116 lists the bit assignment of the UARTRSR/

UARTECR register.

Table 115. UARTDR register(1)

Bits

Name

Function

15:12

RESERVED.

Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full.

This is cleared to 0 once there is an empty space in the FIFO and a new character can be written

to it.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data

input was held LOW for longer than a full-word transmission time (defined as start, data, parity

and stop bits).

In the FIFO mode, this error is associated with the character at the top of the FIFO. When a break

occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the

receive data input goes to HIGH (marking state), and the next valid start bit is received.

9PE

Parity error. When set to 1, it indicates that the parity of the received data character does not

match the parity that the EPS and SPS bits in the line control register, UARTLCR_H in

Section 12.6.7 on page 126 select.

In the FIFO mode, this error is associated with the character at the top of the FIFO.

8FE

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit

(a valid stop bit is 1).

In the FIFO mode, this error is associated with the character at the top of the FIFO.

7:0

DATA

Receive (read) data character.

Transmit (write) data character.

You must disable the UART before any of the control registers are reprogrammed. When the UART is disabled in the

middle of transmission or reception, it completes the current character before stopping.

Table 116. UARTRSR/UARTECR register(1)

Bits

Name

Function

7:0

A write to this register clears the framing, parity, break, and overrun errors. The data value is not

important.

7:4

RESERVED, unpredictable when read.

3OE

Overrun error. This bit is set to 1 if data is received and the FIFO is already full.

This bit is cleared to 0 by a write to UARTECR.

The FIFO contents remain valid because no more data is written when the FIFO is full, only the

contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

RM0352 Datasheet(PDF) 121 Page - STMicroelectronics

RM0352 Datasheet(HTML) 121 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL