9

®

DAC7624/7625

1

2

3

4

V

REFH

V

OUTB

Load DAC Registers

V

OUTA

V

SS

5

GND

6

RESET

7

8

9

10

11

12

13

14

LDAC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

V

REFL

V

OUTC

DAC7624

DAC7625

V

OUTD

V

DD

28

27

26

25

NIC

24

CS

23

A0

A1

R/W

DB11

DB10

DB9

DB8

DB7

22

21

20

19

18

17

16

15

Chip Select

–2.5V to +2.5V

–2.5V to +2.5V

Read/Write

Data Bus

Address Bus

or Decoder

NOTE: (1) Reset LOW sets all DACs to code 800

–2.500V

0.1µF

+5V

0.1µF

1µF to 10µF

+

–2.5V to +2.5V

–2.5V to +2.5V

–5V

+2.500V

0.1µF

0.1µF

1µF to 10µF

+

Data Bus

1

2

3

4

V

REFH

V

OUTB

Load DAC Registers

V

OUTA

V

SS

5

GND

6

RESET

7

8

9

10

11

12

13

14

LDAC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

V

REFL

V

OUTC

DAC7624

DAC7625

V

OUTD

V

DD

28

27

26

25

NIC

24

CS

23

A0

A1

R/W

DB11

DB10

DB9

DB8

DB7

22

21

20

19

18

17

16

15

Chip Select

Read/Write

Data Bus

Data Bus

Address Bus

or Decoder

+5V

NOTE: (1) Reset LOW sets all DACs to code 800

0V to +2.5V

0V to +2.5V

0V to +2.5V

0V to +2.5V

0.1µF

1µF to 10µF

+

+2.500V

0.1µF

THEORY OF OPERATION

The DAC7624 and DAC7625 are quad, voltage output,

12-bit digital-to-analog converters (DACs). The architecture

is a classic R-2R ladder configuration followed by an opera-

tional amplifier that serves as a buffer. Each DAC has its

own R-2R ladder network and output op-amp, but all share

the reference voltage inputs. The minimum voltage output

(“zero-scale”) and maximum voltage output (“full-scale”)

respectively). The digital input is a 12-bit parallel word and

the DAC input registers offer a readback capability. The

converters can be powered from a single +5V supply or a

dual

±5V supply. Each device offers a reset function which

immediately sets all DAC output voltages and DAC regis-

operation of the DAC7624/25.

FIGURE 1. Basic Single-Supply Operation of the DAC7624/25.

FIGURE 2. Basic Dual-Supply Operation of the DAC7624/25.