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IO96PDB2V1 Datasheet(PDF) 107 Page - Microsemi Corporation |
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IO96PDB2V1 Datasheet(HTML) 107 Page - Microsemi Corporation |
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107 / 242 page ![]() ProASIC3L Low Power Flash FPGAs Revision 13 2-91 Timing Characteristics Table 2-152 • HSTL Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 2.86 0.04 2.50 0.38 2.91 2.83 4.93 4.84 ns –1 0.50 2.43 0.03 2.12 0.33 2.48 2.41 4.19 4.12 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-153 • HSTL Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 2.86 0.05 2.50 0.50 2.91 2.83 4.93 4.84 ns –1 0.66 2.43 0.04 2.12 0.43 2.48 2.41 4.19 4.12 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. |
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