STM32F217VG datasheet(171/173 Pages) STMICROELECTRONICS

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STM32F21xxx

Revision history

Doc ID 17050 Rev 8

171/173

29-Oct-2012

Removed Figure 4. Compatible board design between STM32F10xx

and STM32F2xx for LQFP176 package.

Updated number of AHB buses in Section 2: Description and

Section 2.2.12: Clocks and startup.

Updated Note 2 below Figure 4: STM32F21x block diagram.

Changed System memory to System memory + OTP in Figure 13:

Memory map.

Added Note 1 below Table 13: VCAP1/VCAP2 operating conditions.

Updated VDDA and VREF+ decouping capacitor in Figure 16: Power

supply scheme and updated Note 3.

Changed simplex mode into half-duplex mode in Section 2.2.24: Inter-

integrated sound (I2S).

Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and

DAC_OUT2, respectively.

Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and PA5

in Table 7: Alternate function mapping.

Updated note applying to IDD (external clock and all peripheral

disabled) in Table 17: Typical and maximum current consumption in

Run mode, code with data processing running from Flash memory

(ART accelerator disabled). Updated Note 3 below Table 19: Typical

and maximum current consumption in Sleep mode.

Removed fHSE_ext typical value in Table 25: High-speed external user

clock characteristics.

Updated master I2S clock jitter conditions and vlaues in Table 32:

PLLI2S (audio PLL) characteristics.

Updated equations in Section 5.3.11: PLL spread spectrum clock

generation (SSCG) characteristics.

Swapped TTL and CMOS port conditions for VOL and VOH in Table 44:

Output voltage characteristics. Updated VIL(NRST) and VIH(NRST) in

Table 46: NRST pin characteristics.

Updated Table 51: SPI characteristics and Table 52: I2S

characteristics.Removed note 1 related to measurement points below

Figure 39: SPI timing diagram - slave mode and CPHA = 1, Figure 40:

SPI timing diagram - master mode, and Figure 41: I2S slave timing

diagram (Philips protocol)(1).

Updated tHC in Table 58: ULPI timing.

Updated Figure 45: Ethernet SMI timing diagram, Table 60: Dynamics

characteristics: Ethernet MAC signals for SMI and Table 61: Dynamics

characteristics: Ethernet MAC signals for RMII.

Update fTRIG in Table 63: ADC characteristics. Updated IDDA

description in Table 65: DAC characteristics.

Updated note below Figure 50: Power supply and reference

decoupling (VREF+ not connected to VDDA) and Figure 51: Power

supply and reference decoupling (VREF+ connected to VDDA).

Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 73: Synchronous

multiplexed NOR/PSRAM read timings, Table 75: Synchronous non-

multiplexed NOR/PSRAM read timings, Figure 57: Synchronous

multiplexed NOR/PSRAM read timings and Figure 59: Synchronous

non-multiplexed NOR/PSRAM read timings.

Table 92.

Document revision history (continued)

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