AM79C971VCW datasheet(234/265 Pages) AMD

234 / 265 page

B-2

Am79C971

The most critical pins in the layout of a Am79C971 de-

sign are the four analog power and two analog ground

pins, VDD_PLL, AVDD, VSS_PLL and AVSS respec-

tively. All of these pins are located in one corner of the

device, the “analog corner.” Specific functions and lay-

out requirements of the analog power and ground pins

are given below.

AVSS and AVDD

These pins provide the power and ground for the

Twisted Pair and AUI drivers. In addition AVSS serves

as the ground for the logic interfaces in the 20 MHz

Crystal Oscillator. Hence, these pins can be very noisy.

A dedicated 0.1

µF capacitor between these pins is

recommended.

VSS_PLL and VDD_PLL

These pins are the most critical p ins on t h e

Am79C971 device because they provide the power

and ground for the phase-lock loop (PLL) portion of the

chip. The voltage-controlled oscillator (VCO) portion of

the PLL is sensitive to noise in the 60 kHz - 200 kHz.

range. To prevent noise in this frequency range from

disrupting the VCO, it is strongly recommended that

the low-pass filter shown below be implemented on

these pins when internal ports are used.This filter is not

needed when MII is used solely.

Figure 2.

Power and Ground Pin Connections

To determine the value for the resistor and capacitor,

the formula is:

R * C

≥ 88

where R is in Ohms and C is in microfarads. Some pos-

sible combinations are given below. To minimize the

voltage drop across the resistor, the R value should not

be more than 10

Ω.

Note: The capacitor used should be tantalum not alu-

minum electrolytic.5.0

VSS_PLL and VDD_PLL/AVDD

These pins provide power and ground for the AUI and

twisted pair receive circuitry. In addition, as mentioned

earlier, VSS_PLL and VDD_PLL provide power and

ground for the phase-lock loop portion of the chip. Ex-

cept for the filter circuit already mentioned, no specific

decoupling is necessary on these pins.

AVDD

AVDD provides power for the control and interface logic

in the PLL. Ground for this logic is provided by digital

ground pins. No specific decoupling is necessary on

this pin.

Special Note for Adapter Cards: In adapter card de-

signs, it is important to utilize all available power

and ground pins available on the bus edge connec-

tor. In addition, the connection from the bus edge con-

nector to the power or ground plane should be made

through more than one via and with wide traces (15

mils desirable) wherever possible. Following these rec-

ommendations results in minimal inductance in the

power and ground paths. By minimizing this induc-

tance, ground bounce is minimized.

See also the PCnet™ Family Board Design and Layout

Recommendations applications note (PID# 19595) for

additional information.

VDD_PLL

VSS_PLL

Am79C971

VDD Plane

µF to 10 µF

0.1

µF

Ω to 10 Ω

VSS Plane

(Pin 129)

(Pin 119)

2.7

Ω το 10 Ω

19364D-2

2.7

Ω

µF

4.3

Ω

µF

6.8

Ω

µF

Ω

µF

AM79C971VCW Datasheet(PDF) 234 Page - Advanced Micro Devices

AM79C971VCW Datasheet(HTML) 234 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL