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OMAP3530ECBBA Datasheet(PDF) 197 Page - Texas Instruments |
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OMAP3530ECBBA Datasheet(HTML) 197 Page - Texas Instruments |
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197 / 264 page  dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] DL4 DL5 DL3 030-062 6.5.2.2 LCD Display in RFBI Mode OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Figure 6-29. LCD Display in STN Mode(1)(2)(3)(4)(5) (1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. (3) dss_vsync width must be programmed to be as small as possible. (4) The pixel clock frequency is programmable. (5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98. Table 6-40 and Table 6-41 assume testing over the recommended operating conditions (see Figure 6-30 through Figure 6-32). Table 6-39. LCD Timing Conditions – RFBI Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Input Conditions tR Input signal rise time 15 ns tF Input signal fall time 15 ns Output Conditions CLOAD Output load capacitance 30 pF Table 6-40. LCD Display Timing Requirements in RFBI Mode NO. PARAMETER OPP3 OPP2 OPP1(1) UNIT MIN MAX MIN MAX MIN MAX DR0 tsu(DAV-RDH) Setup time, rfbi_da[15:0] valid to rfbi_rd 7.0 9.0 ns high DR1 th(RDH-DAIV) Hold time, rfbi_rd high to rfbi_da[15:0] 5.0 5.0 ns invalid td(Data sampled) rfbi_da[15:0] are sampled at the end off N(2) N(2) ns the access time (1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. (2) N = (AccessTime) * (TimeParaGranularity + 1) * L4CLK Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 197 |
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