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KS0073 Datasheet(PDF) 47 Page - Samsung semiconductor

No. de pieza KS0073
Descripción Electrónicos  34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Download  78 Pages
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Fabricante Electrónico  SAMSUNG [Samsung semiconductor]
Página de inicio  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KS0073 Datasheet(HTML) 47 Page - Samsung semiconductor

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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
47
13) Read Busy Flag & Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether S6A0073 is in internal operation or not. If the resultant BF is High, the internal
operation is in progress and should wait until BF becomes "LOW", which by then the next instruction can be
performed. In this instruction value of address counter can also be read.
14) Write data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.
The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction :
DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the
AC direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
15) Read data from RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not determined.
If the RAM data several is read times without RAM address set instruction before read operation, the correct
RAM data from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set
instruction : it also transfer RAM data to output data register.
After read operation address counter is automatically increased/decreased by 1 according to the entry mode.
After CGRAM/SEGRAM read operation, display shift may not be executed correctly.
* In case of RAM write operation, after this AC is increased/decreased by 1 as in read operation after this. In this
time, AC indicates the next address position, but the previous data can only be read by read instruction.


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