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KS0127 Datasheet(PDF) 10 Page - Samsung semiconductor |
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KS0127 Datasheet(HTML) 10 Page - Samsung semiconductor |
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10 / 96 page  ELECTRONICS KS0127B Data Sheet MULTIMEDIA VIDEO PAGE 10 OF 96 Modified on May/04/2000 CMDD register. Timing selection is through either SYNDIR or EAV bit. Figure 3. 8-bit YCbCr Input Data Path By using an external pixel clock, the reference clock input at XTALI is no longer required. Additional register bits have to be programmed for different selections of pixel clock and timing, which are detailed in Table 2. The following register/bit-settings are required for digital video input: INSEL[3:0] = 8, 9, A, or F. TSTCGN = 1. DMCTL[1:0] = 2 or 3. UGAIN = 238. BRT = 34. SAT = 229. RGBH = UNIT = PED = 1. Table 2: Digital Video Input Pixel Clock and Timing Selection Pixel Clock TTL Timing Embedded Timing Additional Register Programming CKDIR*1 SYNDIR*2 EAV*3 VMEN TSTGPH TSTGEN TSTGFR PIXSEL MNFMT IFMT 0 0 0 1 0 1 3 0 if input data is at square pixel rate. 1 if input is at CCIR 601 rate. 1 0 if input is 50 Hz video. 1 if input is 60 Hz video. 0 0 1 0 1 1 3 1 0 1 0 0 1 1 1 1 1 0 0 1 0 1 3 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 *1: CKDIR = 0 - CK is output and is internally generated. CKDIR = 1 - CK is input from an external source. *2: SYNDIR = 0 - HS1 and VS are output. SYNDIR = 1 - HS1 and VS are inputs from external sources. *3: EAV = 0 - chip will not sync to embedded timing. EAV = 1 - chip will sync to embedded timing. Note: the combination X11 for CKDIR, SYNDIR, EAV is not valid. HS1 VS EXV[7:0] Timing Control Data Demux Y C Luma Processing Chroma Processing From Luma ADC From Chroma ADC To Luma Scaler To Chroma Scaler |
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