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PC912XDP512F0CFVR Datasheet(PDF) 279 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0CFVR Datasheet(HTML) 279 Page - Freescale Semiconductor, Inc |
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279 / 1348 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 279 Operation RS ⇒ M[RB, #OFFS5] RS ⇒ M[RB, RI] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI]1 Stores the content of register RS to memory. CCR Effects Code and CPU Cycles STW Store Word to Memory STW 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS NZ V C ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles STW RS, (RB, #OFFS5) IDO5 0 1 0 1 1 RS RB OFFS5 PW STW RS, (RB, RI) IDR 0 1 1 1 1 RS RB RI 0 0 PW STW RS, (RB, RI+) IDR+ 0 1 1 1 1 RS RB RI 0 1 PW STW RS, (RB, -RI) -IDR 0 1 1 1 1 RS RB RI 1 0 PW |
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