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PCIMX258CJM4A Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 113 Figure 83 shows the timing for ADC normal operation. Figure 83. Timing for ADC Normal Operation When the ADC is used so that the idle clock cycles occur between conversions (due to the negation of soc), the selin inputs must be stable at least 1 clock cycle before the clock's rising edge where the soc signal is latched. Also, selrefp and selrefn must be stable by the time the soc signal is latched. These conditions are met if enadc=1 and reset=0 throughout ADC operation, including the idle cycles. If the conditions are not met, or if power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again. |
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