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ATmega165 Datasheet(PDF) 283 Page - ATMEL Corporation |
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ATmega165 Datasheet(HTML) 283 Page - ATMEL Corporation |
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283 / 336 page ![]() 283 ATmega165/V 2573G–AVR–07/09 Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK > 12 MHz Figure 130. SPI Interface Timing Requirements (Master Mode) Figure 131. SPI Interface Timing Requirements (Slave Mode) 13 Setup Slave 10 ns 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 • tck Table 118. SPI Timing Parameters Description Mode Min Typ Max MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 MISO (Data Output) SCK (CPOL = 1) MOSI (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 10 11 11 12 13 14 17 15 9 X 16 |
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