3

0015O–EPROM–12/07

AT27C512R

3.

System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce tran-

sient voltage excursions. Unless accommodated by the system design, these transients may

exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high

frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This

capacitor should be connected between the V

to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit

boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again

connected between the V

close as possible to the point where the power supply is connected to the array.

4.

Block Diagram

Note:

1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is

V

5.

Absolute Maximum Ratings*

Temperature Under Bias............................... -55°C to + 125°C

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only and func-

tional operation of the device at these or any other

conditions beyond those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Storage Temperature .................................... -65°C to + 150°C

Voltage on Any Pin with

Respect to Ground ........................................-2.0V to + 7.0V(1)

Voltage on A9 with

Respect to Ground .....................................-2.0V to + 14.0V(1)

Respect to Ground ......................................-2.0V to + 14.0V(1)