M38044FFHKP datasheet(201/387 Pages) RENESAS

201 / 387 page

2-77

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Serial I/O1 status register (Address : 001916)

SIO1STS

Transmitting side

Baud rate generator 1 (Address : 001C16)

BRG1

8 – 1

SIO1CON 1

00 1

0 1

UART1 control register (Address : 001B16)

UART1CON

f(XIN)

Transfer bit rate ✕ 16 ✕ m

–1

Serial I/O1 control register (Address : 001A16)

Set

When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,”

a value of m is 1.

When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,”

a value of m is 4.

✽

BRG count source : f(XIN)/4

Synchronous clock : BRG/16

Transmit enabled

Receive disabled

Asynchronous serial I/O(UART)

Serial I/O1 enabled

SRDY1

output disabled

Character length : 8 bits

Parity checking disabled

P45/TXD1 pin : CMOS output

Stop bit length : 2 stop bits

Transmit buffer empty flag

• Confirm that the data has been transferred from Transmit buffer

• When this flag is “1”, it is possible to write the next transmission

data in to Transmit buffer register.

Transmit shift register shift completion flag

Confirm completion of transmitting 1-byte data with this flag.

“1” : Transmit shift completed

Port P40: Communication control: “H” active

Port P4 (Address : 000816)

Port P40: Communication control: Output mode

P4D

Port P4 direction register (Address : 000916)

Fig. 2.4.40 Registers setting relevant to transmitting side

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