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M38044FFHKP Datasheet(PDF) 174 Page - Renesas Technology Corp |
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M38044FFHKP Datasheet(HTML) 174 Page - Renesas Technology Corp |
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174 / 387 page ![]() 2-50 APPLICATION 2.4 Serial interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.4.5 Structure of Serial I/O3 control register Serial I/O3 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O3 control register (SIO3CON: address 003216) b 0 Name 0 Functions At reset R W 0 0 1 2 0 3 Transmit interrupt source selection bit (TIC) 4 0 Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled 0: I/O port (P37) 1: SRDY3 output pin 0: Receive disabled 1: Receive enabled 0: UART 1: Clock synchronous serial I/O 5 0 Receive enable bit (RE) 7 6 0 Serial I/O3 mode selection bit (SIOM) Serial I/O3 enable bit (SIOE) 0: Transmit buffer empty 1: Transmit shift operation completion 0: f(XIN) 1: f(XIN)/4 When clock synchronous serial I/O is selected, 0: BRG output divided by 4 1: External clock input When UART is selected, 0: BRG output divided by 16 1: External clock input divided by16 0: Serial I/O3 disabled (P34 to P37: normal I/O pins) 1: Serial I/O3 enabled (P34 to P37: Serial I/O pins) Serial I/O3 synchronous clock selection bit (SCS) BRG count source selection bit (CSS) SRDY3 output enable bit (SRDY) 0 |
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