M38041FFHKP datasheet(270/387 Pages) RENESAS

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APPLICATION

2.11

Clock generating circuit

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

2.11.2 Clock generating circuit application example

(1)

Status transition during power failure

Outline: The clock counts up every second by using the timer interrupt during a power failure.

Fig. 2.11.2 Connection diagram

Specifications: •Reducing power dissipation as low as possible while maintaining clock function

•Clock: f(XIN) = 8 MHz, f(XCIN) = 32.768 kHz

•Port processing

Input port: Fixed to “H” or “L” level externally.

Output port: Fixed to output level that does not cause current flow to the external.

(Example) Fix to “H” for an LED circuit that turns on at “L” output

level.

I/O port: Input port

→ Fixed to “H” or “L” level externally.

Output port

→ Output of data that does not consume current

VREF pin: Terminate A/D conversion operation

Stop VREF current dissipation by setting value of DAi conversion register

to “0016”.

Figure 2.11.3 shows the status transition diagram during power failure and Figure 2.11.4 shows the

setting of relevant registers.

Fig. 2.11.3 Status transition diagram during power failure

3804 Group (Spec. H)

Input port

(Note)

Power failure detection signal

Note: A signal is detected when input to input port, interrupt

input pin, or analog input pin.

Reset released

Power failure detected

Internal system clock

XCIN

XIN

Middle-speed

mode

High-speed mode

Low-speed mode

Change internal system

clock to high-speed mode

After detection, change internal system clock to

low-speed mode and stop oscillating XIN-XOUT

XCIN-XCOUT oscillation function selected

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