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M38047F9HKP Datasheet(PDF) 215 Page - Renesas Technology Corp |
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M38047F9HKP Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 387 page ![]() 2-91 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.5.10 Structure of I2C slave address register i (i = 0 to 2) I2C slave address register i (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 I2C slave address register i (i = 0 to 2) (S0D0, S0D1, S0D2: addresses 0FF716, 0FF816, 0FF916) b 0 0 Read/Write bit (RWB) 0: Write bit 1: Read bit The contents of these bits are compared with the address data transmitted from master. Functions Name At reset R W 1 0 2 0 3 0 4 0 5 0 6 0 7 0 Slave address (SAD0, SAD1, SAD2, SAD3, SAD4, SAD5, SAD6) Note: When the read-modify-write instructions (SEB, CLB) are used at detection of stop condition, the values may be undefined. Fig. 2.5.11 Structure of Interrupt source selection register Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) 0: INT0 interrupt 1: Timer Z interrupt b 0 1 4 2 3 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 INT0/Timer Z interrupt source selection bit (*1) 0: Serial I/O2 interrupt 1: Timer Z interrupt Serial I/O2/Timer Z interrupt source selection bit (*1) 0: INT4 interrupt 1: CNTR2 interrupt INT4/CNTR2 interrupt source selection bit 0: INT2 interrupt 1: I2C interrupt INT2/I2C interrupt source selection bit 0: CNTR0 interrupt 1: SCL, SDA interrupt CNTR0/SCL, SDA interrupt source selection bit (*2) 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) CNTR1/Serial I/O3 receive interrupt source selection bit AD converter/Serial I/O3 transmit interrupt source selection bit *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. 0 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt |
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