M38049F8HKP datasheet(140/387 Pages) RENESAS

140 / 387 page

2-16

APPLICATION

2.2 Interrupt

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

2.2.5 Interrupt control

The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt

request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.12

shows an interrupt control diagram.

Fig. 2.2.12 Interrupt control diagram

The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not

affect each other. An interrupt is accepted when all the following conditions are satisfied.

qInterrupt request bit .......... “1”

qInterrupt enable bit ........... “1”

qInterrupt disable flag ........ “0”

Though the interrupt priority is determined by hardware, a variety of priority processing can be performed

by software using the above bits and flag. Tables 2.2.2 shows list of interrupt control bits according to the

interrupt source.

(1)

Interrupt request bits

The interrupt request bits are allocated to the interrupt request register 1 (address 003C16) and

interrupt request register 2 (address 003D16).

The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to

“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt

is accepted, this bit is automatically cleared to “0”.

Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.

(2)

Interrupt enable bits

The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the

interrupt control register 2 (address 003F16).

The interrupt enable bits control the acceptance of the corresponding interrupt request.

When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt

request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the

interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the

interrupt request bit remains in the “1” state.

When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request

occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).

Each interrupt enable bit can be set to “0” or “1” by software.

Interrupt request bit

Interrupt enable bit

Interrupt disable flag

BRK instruction

Reset

Interrupt request

M38049F8HKP Datasheet(PDF) 140 Page - Renesas Technology Corp

M38049F8HKP Datasheet(HTML) 140 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL