M38043F6HKP datasheet(101/387 Pages) RENESAS

101 / 387 page

1-83

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Fig. 81 CPU rewrite mode set/release flowchart

Figure 81 shows a flowchart for setting/releasing CPU rewrite

mode.

Fig. 80 Structure of flash memory control register 2

Table 14 State of E/W inhibition function

All user block E/W

enable bit

8 KB user block E/W

enable bit

8 KB ✕ 2 block

Addresses C00016 to FFFF16

E/W disabled

E/W enabled

16 KB + 24 KB block

Addresses 200016 to BFFF16

E/W disabled

E/W enabled

Data block

Addresses 100016 to 1FFF16

E/W enabled

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a

“1” to it in succession. For this bit to be set to “0”, write “0” only to

this bit.

2: Effective only when the CPU rewrite mode select bit = “1”.

Not used

Not used (do not write “1” to this bit.)

All user block E/W enable bit (Notes 1, 2)

0 :

E/W disabled

1 :

E/W enabled

Flash memory control register 2

(FMCR2: address : 0FE216: initial value: 4516)

Not used

End

Start

Execute read array command (Note 2)

Single-chip mode or Boot mode

Set CPU mode register (Note 1)

Using software command executes erase,

program, or other operation

Jump to control program transferred to internal

RAM

(Subsequent operations are executed by control

program in this RAM)

Transfer CPU rewrite mode control program to

internal RAM

Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU

mode register (bits 6, 7 of address 003B16).

2: Before exiting the CPU rewrite mode after completing erase or program operation, always

be sure to execute the read array command.

Write “0” to CPU rewrite mode select bit

Set CPU rewrite mode select bit to “1” (by

writing “0” and then “1” in succession)

Set all user block E/W enable bit to “1”

(by writing “0” and then “1” in succession)

Set 8 KB user block E/W enable bit

(At E/W disabled; writing “0”, at E/W enabled;

writing “0” and then “1” in succession)

Set all user block E/W enable bit to “0”

Set 8 KB user block E/W enable bit to “0”

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