M38045F2HKP datasheet(223/387 Pages) RENESAS

223 / 387 page

2-99

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.5.20 Initial setting example for SMBUS communication

S0D0

0 01 0

0 00 1

S2D

S1D

I2C slave address register 0 (address 0FF716)

I2C clock control register (address 001516)

I2C status register (address 001316)

I2C START/STOP condition control register (address 001616)

I2C control register (address 001416)

Set slave address value 001616.

Set clock 100 kHz (XIN = 8MHz)

Standard clock mode

ACK is returned

ACK clock

SCL pin low hold bit: Fix to “1”

Slave receive mode

Set setup time, hold time to 27 cycles (6.75

µs: XIN = 8 MHz).

SCL/SDA interrupt: Falling edge active

SCL/SDA interrupt: SDA valid

Fix to “0”

Set number of transmit/receive bits to “8”.

I2C-BUS interface: Enabled

Addressing format

7-bit addressing format

Fix to “0”

Set SMBUS input level.

S3D

0 0

I2C special mode control register (address 001716)

Fix to “0”

ACK interrupt control : At communication completion

One-byte slave address compare mode

Fix to “0”

SCL pin low hold 2 flag set bit : Not used

SCL pin low hold set bit : Not set

STOP condition flag clear bit : Not used

This setting can be omitted.

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