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M38044F2HKP Datasheet(PDF) 271 Page - Renesas Technology Corp |
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M38044F2HKP Datasheet(HTML) 271 Page - Renesas Technology Corp |
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271 / 387 page ![]() 2-147 APPLICATION 2.11 Clock generating circuit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.11.4 Setting of relevant registers b7 b0 CPU mode register (CPUM) (address 003B16) Main clock: High-speed mode (f(XIN)/2) (Note 1) 0 b7 b0 CPUM 00 01 0 0 CPUM 0 01 01 0 0 CPU mode register (CPUM) (address 003B16) Port XC: XCIN–XCOUT oscillation function (Note 2) b7 b0 10 0 Internal system clock: Low-speed mode (f(XCIN)/2) CPUM CPU mode register (CPUM) (address 003B16) 11 0 0 b7 b0 1 0 CPUM CPU mode register (CPUM) (address 003B16) 11 0 0 1 Main clock f(XIN): Stopped Notes 1: This setting is necessary only when selecting the high-speed mode. 2: When selecting the middle-speed mode, bit 6 is “1”. |
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