SH7708 datasheet(203/633 Pages) RENESAS

203 / 633 page

185

CAP2

VCC (PLL2)

VCC (PLL1)

VCC

C1 = 470 pF

C2 = 470 pF

VSS

CAP1

VSS (PLL2)

VSS (PLL1)

Avoid crossing

signal lines

Power supply

Reference values

Figure 9.9 Points for Attention when Using PLL Oscillator Circuit

Power Supply Pin Wiring: To prevent mutual interference between power supply pins V

(PLL1), V

CC (PLL2) and power supply pins VSS (PLL1), VSS (PLL2), use independent wiring

patterns for these two systems, and also other digital V

CC and VSS pins, from the board power

supply source.

External Device Connection: When connecting a device such as synchronous DRAM that

requires timing adjustment, since the AC characteristics are based on the connection of a 30 pF

capacitive load to the CKIO output, the total capacitive load of CKIO should be 30 pF or less. If

the total capacitive load of the CKIO output exceeds 30 pF, a device requiring timing adjustment

should be connected directly to CKIO, while in the case of a device without stringent timing

adjustment requirements, the CKIO output should be received by a buffer to allow the total

capacitive load of the CKIO output to be reduced.

SH-3

CKIO

SDRAM

CKIO total capacitive load

≤ 30 pF

Clock driver

G/A

Figure 9.10 System Connection Example

SH7708 Datasheet(PDF) 203 Page - Renesas Technology Corp