 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
SH7708 Datasheet(PDF) 176 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7708 Datasheet(HTML) 176 Page - Renesas Technology Corp |
|
|
176 / 633 page  158 9.2 Overview of the CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S) and figure 9.2(SH7708R). CAP1 CKIO Cycle = Bcyc CAP2 XTAL EXTAL MD2 MD1 MD0 FRQCR Internal bus Bus interface STBCR PLL circuit 1 ( × 1, 2, 4) Divider 1 Internal clock (I φ) Cycle = Icyc Peripheral clock (P φ) Cycle = Pcyc Standby control Divider 2 Clock pulse generator PLL circuit 2 ( × 1, 4) Crystal oscillator CPG control unit Clock frequency control circuit Standby control circuit × 1 × 1/2 × 1/4 × 1 × 1/2 × 1/4 FRQCR: Frequency control register STBCR: Standby control register Figure 9.1 Block Diagram of Clock Pulse Generator(SH7708, SH7708S) |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
