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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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SH7708 Datasheet(PDF) 154 Page - Renesas Technology Corp |
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SH7708 Datasheet(HTML) 154 Page - Renesas Technology Corp |
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154 / 633 page  136 7.3.3 Data Access Cycle Break 1. In the case of a data access cycle break, the bits used for comparison with the address bus depend on the break bus cycle register (BBRA/BBRB) operand size specification, as follows: Operand size Compared address Not included in conditions (00): For byte address, comparison with address bits A31–A0 For word address, comparison with address bits A31–A1 For longword address, comparison with address bits A31–A2 Byte (01): Comparison with address bits A31–A0 Word (10): Comparison with address bits A31–A1 Longword (11): Comparison with address bits A31–A2 2. When data value is included in break condition in channel B When the data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are needed in addition to the address condition. A user break trap is generated on a match of the address condition and the data condition. Bits IDB1 and IDB0 of break bus cycle register B (BBRB) should be set to 00 or 01. When byte data is specified, set the same data in the two bytes comprising bits 15–8 and bits 7–0 in break data register B (BDRB) and break mask register B (BDMRB). If word or byte is designated, bits 31–16 of BDRB and BDMRB are ignored. |
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