SH7708 datasheet(132/633 Pages) RENESAS

132 / 633 page

114

Table 6.4

Interrupt Exception Vectors and Rankings (cont)

Interrupt Source

INTEVT

Code

Interrupt Priority

(Initial Value)

IPR (Bit

Numbers)

Priority within

IPR Setting Unit

Default

Priority

RTC

ATI*3

H'480

0–15 (0)

IPRA (3–0)

High

RTC

PRI*4

H'4A0

0–15 (0)

IPRA (3–0)

↓

RTC

CUI*5

H'4C0

0–15 (0)

IPRA (3–0)

Low

SCI

ERI*6

H'4E0

0–15 (0)

IPRB (7–4)

High

SCI

RXI*7

H'500

0–15 (0)

IPRB (7–4)

↓

SCI

TXI*8

H'520

0–15 (0)

IPRB (7–4)

SCI

TEI*9

H'540

0–15 (0)

IPRB (7–4)

Low

WDT

ITI

H'560

0–15 (0)

IPRB (15–12)

—

REF

RCMI*10

H'580

0–15 (0)

IPRB (11–8)

High

REF

ROVI*11

H'5A0

0–15 (0)

IPRB (11–8)

Low

Notes: 1. TUNI0–TUNI2: Underflow interrupts, see section 11.

2. TICPI2: Input capture interrupt, see section 11.

3. ATI: Alarm interrupt, see section 12.

4. PRI: Periodic interrupt, see section 12.

5. CUI: Carry-up interrupt, see section 12.

6. ERI: Receive error interrupt, see section 13.

7. RXI: Receive-data-full interrupt, see section 13.

8. TXI: Transmit-data-empty interrupt, see section 13.

9. TEI: Transmit-data-end interrupt, see section 13.

10. ITI: Interval timer interrupt, see section 9.

11. RCMI: Compare-match interrupt, see section 10.

12. ROVI: Refresh counter overflow interrupt, see section 10.

SH7708 Datasheet(PDF) 132 Page - Renesas Technology Corp

SH7708 Datasheet(HTML) 132 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL