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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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SH7052 Datasheet(PDF) 101 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 101 Page - Renesas Technology Corp |
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101 / 919 page  75 Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features The INTC has the following features: • 16 levels of interrupt priority By setting the twelve interrupt-priority level registers, the priorities of IRQ interrupts and on- chip peripheral module interrupts can be set in 16 levels for different request sources. • NMI noise canceler function NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. |
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