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H8SX/1663R Datasheet(PDF) 243 Page - Renesas Technology Corp

No. de pieza H8SX/1663R
Descripción Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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H8SX/1663R Datasheet(HTML) 243 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 211 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
Value
R/W
Description
4
EDDS
0
R/W
EXDMAC Single Address Transfer Option
Selects whether an EXDMAC single address transfer
through the DRAM/SDRAM interface is enabled only in
full access mode or is also enabled in fast-page access
mode.
When clearing the BE bit to 0 to disable a burst access
to the DRAM/SDRAM interface, an EXDMAC single
address transfer is performed in full access mode
regardless of this bit.
This bit does not affect an external access by other bus
masters or an EXDMAC dual address transfer. Setting
this bit to 1 changes the EDACK output timing.
0: EXDMAC single address transfer through the
DRAM/SDRAM is enabled only in full access mode
1: EXDMAC single address transfer through the
DRAM/SDRAM is also enabled in fast-page access
mode
3
2
0
0
R
R/W
Reserved
The initial value should not be changed.



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