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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H8SX/1663R Datasheet(PDF) 871 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 871 Page - Renesas Technology Corp |
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871 / 1504 page  Section 16 8-Bit Timers (TMR) Rev. 2.00 Sep. 24, 2008 Page 839 of 1468 REJ09B0412-0200 16.8 Usage Notes 16.8.1 Notes on Setting Cycle If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula. f = φ / (N + 1 ) f: Counter frequency φ: Operating frequency N: TCOR value 16.8.2 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T 2 state of a TCNT write cycle, the clear takes priority and the write is not performed as shown in figure 16.15. P φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 T 1 T 2 TCNT write cycle by CPU Figure 16.15 Conflict between TCNT Write and Clear |
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