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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H8SX/1663R Datasheet(PDF) 800 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 800 Page - Renesas Technology Corp |
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800 / 1504 page  Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Sep. 24, 2008 Page 768 of 1468 REJ09B0412-0200 14.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = P φ (N + 1) f: P φ: N: Counter frequency Operating frequency TGR set value 14.10.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 14.47 shows the timing in this case. Counter clear signal H'0000 P φ TCNT N Address Write T 1 T 2 TCNT address TCNT write cycle Figure 14.47 Conflict between TCNT Write and Clear Operations |
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