H8SXSLASH1663R datasheet(754/1504 Pages) RENESAS

754 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 722 of 1468

REJ09B0412-0200

14.3.4

Timer Interrupt Enable Register (TIER)

TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER

registers, one for each channel.

Bit

Bit Name

Initial Value

R/W

TTGE*

R/W



TCIEU

R/W

TCIEV

R/W

TGIED

R/W

TGIEC

R/W

TGIEB

R/W

TGIEA

R/W

Note: *

Bit 7 in TIER of unit 1 is a reserved bit.

This bit is always read as 0 and the initial value should not be changed.

Bit

Bit Name

Initial

value

R/W

Description

TTGE*

R/W

A/D Conversion Start Request Enable

Enables/disables generation of A/D conversion start

requests by TGRA input capture/compare match.

0: A/D conversion start request generation disabled

1: A/D conversion start request generation enabled



Reserved

This bit is always read as 1 and cannot be modified.

TCIEU

R/W

Underflow Interrupt Enable

Enables/disables interrupt requests (TCIU) by the TCFU

flag when the TCFU flag in TSR is set to 1 in channels 1,

2, 4, and 5.

In channels 0 and 3, bit 5 is reserved. It is always read as

0 and cannot be modified.

0: Interrupt requests (TCIU) by TCFU disabled

1: Interrupt requests (TCIU) by TCFU enabled

TCIEV

R/W

Overflow Interrupt Enable

Enables/disables interrupt requests (TCIV) by the TCFV

flag when the TCFV flag in TSR is set to 1.

0: Interrupt requests (TCIV) by TCFV disabled

1: Interrupt requests (TCIV) by TCFV enabled

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