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H8SX/1663R Datasheet(PDF) 441 Page - Renesas Technology Corp

No. de pieza H8SX/1663R
Descripción Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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H8SX/1663R Datasheet(HTML) 441 Page - Renesas Technology Corp

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Section 10 DMA Controller (DMAC)
Rev. 2.00 Sep. 24, 2008 Page 409 of 1468
REJ09B0412-0200
Figure 10.10 shows an example of the DMA transfer timing in block transfer mode. The transfer
conditions are as follows:
• Address mode: single address mode
• Data access size: byte
• 1-block size: three bytes
The block transfer mode operations in single address mode and in dual address mode are shown in
figures 10.11 and 10.12, respectively.
CPU
CPU
DMAC
DMAC
DMAC
CPU
Bus cycle
TEND
DREQ
No CPU cycle generated
Transfer cycles for one block
Figure 10.10 Operations in Block Transfer Mode
Transfer
Address T
Address B
DACK
Block
BKSZH
×
data access size
Figure 10.11 Operation in Single Address Mode in Block Transfer Mode
(Block Area Specified)



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