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H8SX/1663R Datasheet(PDF) 349 Page - Renesas Technology Corp

No. de pieza H8SX/1663R
Descripción Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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H8SX/1663R Datasheet(HTML) 349 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 317 of 1468
REJ09B0412-0200
9.11.9
Controlling Clock Suspend Insertion
When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using
the clock suspend mode. To enter the clock suspend mode, set the CKSPE bit in SDCR and the
OEE bit in DRAMCR to 1and enable the CKE pin.
Figure 9.67 shows a read timing example when CKSPE = 1.
T
p
T
r
T
c1
T
cl
T
c2
T
c1
T
cl
T
c2
T
sp
T
sp
SDRAM
φ
CS
Precharge-sel
Address bus
Row address
Row
address
Column address 1
Column address 2
RAS
CAS
WE
CKE
PALL
ACTV
READ
READ
NOP
NOP
DQMLU
DQMLL
D7 to D0
BS
RD/
WR
D15 to D8
Figure 9.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2)



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