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HD6432351 Datasheet(PDF) 288 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 288 Page - Renesas Technology Corp |
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288 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 254 of 988 REJ09B0330-0300 Address TA Address BA Transfer Address TB Address BB 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Notes: Address Address Address Address Where : = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (M•N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL TA TB BA BB LA LB N M Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) |
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