HD6432351 datasheet(227/1025 Pages) RENESAS

No. de pieza	HD6432351

Descripción Electrónicos	16-Bit Single-Chip Microcomputer

PDF	1025 Pages

Scroll/Zoom	100%

Fabricante Electrónico	RENESAS [Renesas Technology Corp]

Página de inicio	http://www.renesas.com

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227 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 193 of 988

REJ09B0330-0300

6.11.4

External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle. The

RD signal,

DRAM interface

RAS and CAS signals remain low until the end of the external bus cycle.

Therefore, when external bus release is performed, the

RD, RAS, and CAS signals may change

from the low level to the high-impedance state.

6.12

Resets and the Bus Controller

In a power-on reset, the H8S/2350, including the bus controller, enters the reset state at that point,

and an executing bus cycle is discontinued.

In a manual reset, the bus controller’s registers and internal state are maintained, and an executing

external bus cycle is completed. In this case,

WAIT input is ignored. Also, since the DMAC is

initialized by a manual reset,

DACK and TEND output is disabled and these pins become I/O

ports controlled by DDR and DR.

HD6432351 Datasheet(PDF) 227 Page - Renesas Technology Corp