H8S2245 datasheet(154/818 Pages) RENESAS

154 / 818 page

Section 5 Interrupt Controller

Rev.3.00 Mar. 26, 2007 Page 112 of 772

REJ09B0355-0300

IRQn

input pin

IRQnF

Note: n = 7 to 0

Figure 5.3 Timing of Setting IRQnF

The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.

Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for

input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0 and use the pin as an I/O pin for another function. Interrupt request flags

IRQ7 to IRQ0 are set when the setting condition is met, regardless of the IER setting, and

therefore only the necessary flags should be checked.

5.3.2

Internal Interrupts

There are 34 sources for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If any one of these is set to

1, an interrupt request is issued to the interrupt controller.

• The interrupt control level can be set by means of ICR.

• The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the

DTC is activated by an interrupt, it is not affected by the interrupt control mode and interrupt

mask bits.

5.3.3

Interrupt Exception Handling Vector Table

Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the ICR. The situation when two or more

modules are set to the same priority, and priorities within a module, are fixed as shown in table

5.4.

H8S2245 Datasheet(PDF) 154 Page - Renesas Technology Corp