H8S2245 datasheet(135/818 Pages) RENESAS

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Section 4 Exception Handling

Rev.3.00 Mar. 26, 2007 Page 93 of 772

REJ09B0355-0300

Section 4 Exception Handling

4.1

Overview

4.1.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.

Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions

are accepted at all times, in the program execution state. See appendix D.1, Port States in Each

Mode.

Exception handling sources, the stack structure, and the operation of the CPU vary depending on

the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.

Table 4.1

Exception Handling Types and Priority

Priority

Exception Handling Type

Start of Exception Handling

High

Reset

Starts immediately after a low-to-high transition at

the

RES pin, or when the watchdog timer overflows.

Interrupt

Starts when execution of the current instruction or

exception handling ends, if an interrupt request has

been issued*

Low

Trap instruction (TRAPA)*

Started by execution of a trap instruction (TRAPA)

Notes: 1. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

2. Trap instruction exception handling requests are accepted at all times in program

execution state.

4.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:

1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.

2. The interrupt mask bits are updated.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

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