H8S2245 datasheet(124/818 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.3.00 Mar. 26, 2007 Page 82 of 772

REJ09B0355-0300

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

External address

space

On-chip ROM

On-chip RAM*3

Notes:

Internal I/O registers

On-chip ROM

External address

space

External address

space

On-chip RAM*3

Reserved area*3

On-chip RAM

Internal I/O registers

External address

space

External address

space

Internal I/O registers

External address

space

H'000000

H'01FFFF

H'020000

H'FFDC00

H'FFFBFF

H'FFFC00

H'FFFFFF

H'FFDC00

H'FFEC00

H'FFFBFF

H'FFFC00

H'FFFFFF

H'01FFFF

H'FFEC00

H'FFFBFF

H'FFFFFF

H'FFFF08

H'FFFE40

H'FFFF07

H'FFFF28

On-chip ROM/

external address

space*1

On-chip ROM/

reserved area*2

H'FFFE3F

H'00FFFF

H'010000

H'00FFFF

H'010000

When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE

bit is cleared to 0, it is on-chip ROM.

This area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when

the EAE bit is cleared to 0.

External addresses can be accessed by clearing the RAME bit in SYSCR to 0.

Figure 3.2 H8S/2245 Memory Map in Each Operating Mode (cont)

H8S2245 Datasheet(PDF) 124 Page - Renesas Technology Corp

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