H8S2245 datasheet(116/818 Pages) RENESAS

No. de pieza	H8S2245

Descripción Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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Section 3 MCU Operating Modes

Rev.3.00 Mar. 26, 2007 Page 74 of 772

REJ09B0355-0300

Bit 6—Reserved: Read-only bit, always read as 0.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control

mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,

Interrupt Control Modes and Interrupt Operation.

Bit 5

Bit 4

INTM1

INTM0

Interrupt

Control Mode

Description

Control of interrupts by I bit

(Initial value)

Control of interrupts by I bit, U bit, and ICR

—

Setting prohibited

—

Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.

Bit 3

NMIEG

Description

An interrupt is requested at the falling edge of NMI input

(Initial value)

An interrupt is requested at the rising edge of NMI input

Bits 2 and 1—Reserved: Read-only bits, always read as 0.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset status is released. It is not initialized in software standby mode.

Bit 0

RAME

Description

On-chip RAM is disabled

On-chip RAM is enabled

(Initial value)

Note:

When the DTC is used, the RAME bit should not be cleared to 0.

H8S2245 Datasheet(PDF) 116 Page - Renesas Technology Corp