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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H838532H Datasheet(PDF) 323 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 323 Page - Renesas Technology Corp |
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323 / 508 page  Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 303 of 484 REJ09B0436-0100 Bit 1: Reserved (MPBR) Bit 1 is reserved. It is a read-only bit and cannot be modified. Bit 0: Reserved (MPBT) Bit 0 is reserved. The write value should always be 0. 10.2.8 Bit Rate Register (BRR) Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 0 BRR0 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode. Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. |
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