H838532H datasheet(291/508 Pages) RENESAS

No. de pieza	H838532H

Descripción Electrónicos	16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series

PDF	508 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 271 of 484

REJ09B0436-0100

9.6.3

Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (

φ/8192 or

φw/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): φ/8192 is

selected when WDCKS is cleared to 0, and

φw/32 when set to 1. When TCSRWE = 1 in TCSRW,

if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When

the TCW count reaches H'FF, the next clock input causes the watchdog timer to overflow, and an

internal reset signal is generated one reference clock (

φ or φ

SUB) cycle later. The internal reset

signal is output for 512 clock cycles of the

OSC clock. It is possible to write to TCW, causing TCW

to count up from the written value. The overflow period can be set in the range from 1 to 256 input

clocks, depending on the value written in TCW.

Figure 9.18 shows an example of watchdog timer operations.

H838532H Datasheet(PDF) 291 Page - Renesas Technology Corp