M32CSLASH8B datasheet(319/406 Pages) RENESAS

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Under development

M32C/8B Group

23. Flash Memory

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 302 of 385

Figure 23.3

FMR2 and FMR3 Registers

b7 b6 b5 b4

Symbol

FMR2

Address

0052h

After Reset

XXXX XXX0b

Function

Bit Symbol

Bit Name

Flash Memory Control Register 2

Reserved bits

−

(b7-b1)

−

Writing to the FMR3 register is enabled.

0: Write disable

1: Write enable

Protect bit

FMR20

Read as undefined value.

b6 b5 b4

Symbol

FMR3

Address

0050h

After Reset

XX0X XX00b

Function

Bit Symbol

Bit Name

−

(b7-b6)

Reserved bit

−

(b5)

Reserved bits

Flash Memory Control Register 3(1)

Lock bit read setting bit

FMR31

Reserved bits

−

(b4-b2)

0: EW0 mode

1: EW1 mode

EW1 mode select bit

FMR30

0: Read via data bus

1: Read by the FMR16 bit in the FMR1 register

Read as undefined value.

Set to 0

Read as undefined value.

NOTE:

1. Write the FMR3 register after the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled) and the FMR20 bit in the

FMR2 register is set to 1 (write enable). After exiting wait mode or stop mode, the FMR3 register becomes the value after reset.

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