M32CSLASH8B datasheet(308/406 Pages) RENESAS

308 / 406 page

Under development

M32C/8B Group

22. Programmable I/O Ports

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 291 of 385

b7 b6 b5 b4

Symbol

PUR0

Address

03F0h

After Reset

00h

Function

Bit Symbol

Bit Name

PU05

PU07

P1_4 to P1_7 pull-up

P3_4 to P3_7 pull-up

PU04

PU03

P2_4 to P2_7 pull-up

P3_0 to P3_3 pull-up

PU06

Pull-Up Control Register 0(1)

P2_0 to P2_3 pull-up

P0_4 to P0_7 pull-up

PU01

P1_0 to P1_3 pull-up

PU02

Pull-up setting for the corresponding ports

0: Not pulled up

1: Pulled up

P0_0 to P0_3 pull-up

PU00

b7 b6 b5 b4

Symbol

PUR1

Address

03F1h

After Reset

XXXX 0000b

Function

Bit Symbol

Bit Name

P5_4 to P5_7 pull-up

−

(b7-b4)

PU13

Pull-Up Control Register 1(1)

Unimplemented.

Write 0. Read as undefined value.

P4_4 to P4_7 pull-up

PU11

P5_0 to P5_3 pull-up

PU12

Pull-up setting for the corresponding ports

0: Not pulled up

1: Pulled up

P4_0 to P4_3 pull-up

PU10

NOTE:

1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as

bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.

NOTE:

1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as

bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.

Figure 22.12

PUR0 Register, PUR1 Register

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