M32CSLASH8B datasheet(270/406 Pages) RENESAS

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M32C/8B Group

18. A/D Converter

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 253 of 385

Figure 18.2

AD0CON0 Register

b7 b6 b5 b4

Symbol

AD0CON0

Address

0396h

After Reset

00h

Function

Bit Symbol

Bit Name

TRG

CKS0

A/D operating mode

select bits 0(2)

Frequency select bit 0

MD1

MD0

Trigger select bit

A/D conversion start bit

ADST

A/D0 Control Register 0(1)

CH1

CH2

b2 b1 b0

0 0 0: ANi_0

0 0 1: ANi_1

0 1 0: ANi_2

0 1 1: ANi_3

1 0 0: ANi_4

1 0 1: ANi_5

1 1 0: ANi_6

1 1 1: ANi_7 (i = none, 0, 2, 15)

Analog input pin

select bits(2, 3)

CH0

When the MSS bit in the AD0CON3 register = 0

b4 b3

0 0: One-shot mode

0 1: Repeat mode

1 0: Single sweep mode

1 1: Repeat sweep mode 0, repeat sweep mode 1

When the MSS bit in the AD0CON3 register = 1

b4 b3

0 0:

0 1:

1 0: Multi-port single sweep mode

1 1: Multi-port repeat sweep mode 0

0: Software trigger

1: External trigger, hardware trigger(4)

0: A/D conversion stops

1: A/D conversion starts(4)

(Note 5)

NOTES:

1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect.

2. Analog input pins must be configured again after an A/D operating mode is changed.

3. Bits CH2 to CH0 are enabled in one-shot mode and repeat mode.

4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after

the TRG bit is set to 1.

φAD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5V.

φAD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5V.

φAD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3

CKS2 bit

in AD0CON3 register

CKS0 bit

in AD0CON0 register

φAD

CKS1 bit

in AD0CON1 register

fAD divided by 4

fAD divided by 3

fAD divided by 2

fAD

fAD divided by 8

fAD divided by 6

Do not set to these values.

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