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M32C/8A Datasheet(PDF) 149 Page - Renesas Technology Corp |
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M32C/8A Datasheet(HTML) 149 Page - Renesas Technology Corp |
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149 / 372 page ![]() M32C/8A Group 13. DMAC Rev.1.00 Jul 15, 2007 Page 132 of 352 REJ09B0385-0100 Figure 13.9 DMA Transfers Triggered by INT Interrupt Requests BCLK DMA0 DMA1 CPU INT0 INT1 DRQ bit in DMA0 DRQ bit in DMA1 Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously and DMA transfers (SFR to RAM) are performed in minimum time. Bus privilege acquired |
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