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M38049F5HKP Datasheet(PDF) 112 Page - Renesas Technology Corp

No. de pieza M38049F5HKP
Descripción Electrónicos  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PDF  116 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38049F5HKP Datasheet(HTML) 112 Page - Renesas Technology Corp

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Rev.1.01
Jan 25, 2005
page 112 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
Table 32 Multi-master I2C-BUS bus line characteristics
Fig. 96 Timing diagram of multi-master I2C-BUS
tBUF
tHD:STA
tHD:DAT
tLOW
tR
tF
tHIGH
tsu:DAT
tsu:STA
tHD:STA
tsu:STO
SCL
P
S
Sr
P
SDA
S: START condition
Sr: RESTART condition
P: STOP condition
Symbol
Parameter
Unit
Bus free time
Hold time for START condition
Hold time for SCL clock = “0”
Rising time of both SCL and SDA signals
Data hold time
Hold time for SCL clock = “1”
Falling time of both SCL and SDA signals
Data setup time
Setup time for repeated START condition
Setup time for STOP condition
tBUF
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
Min.
Max.
Min.
Max.
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
Standard clock mode
High-speed clock mode
Note: Cb = total capacitance of 1 bus line
4.7
4.0
4.7
0
4.0
250
4.7
4.0
1000
300
1.3
0.6
1.3
20+0.1Cb
0
0.6
20+0.1Cb
100
0.6
0.6
300
0.9
300



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