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DAC39RF10 Datasheet(PDF) 117 Page - Texas Instruments

No. de pieza DAC39RF10
Descripción Electrónicos  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Fabricante Electrónico  TI2 [Texas Instruments]
Página de inicio  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 117 Page - Texas Instruments

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or block (64b/66b) boundaries and the multiframe (8b/10b) or multiblock (64b/66b) boundaries to deskew the
Serdes lanes, initializing the link, encoding the data, and monitoring the health of the link.
7.3.7.5 Physical Layer
The devices JESD204C physical layer contains 16 SerDes receivers. Each SerDes lane has a Continuous Time
Linear Equalizer (CTLE) for channel loss equalization.
7.3.7.6 Serdes PLL Control
The Serdes receivers work over a wide frequency range if various parameters are altered. Before setting
JESD_EN, the user must program various parameters for the Serdes receivers to work. The parameters are
adjusted to maintain all these constraints:
1. The VCO clock frequency (FVCO) must be between 1.5625GHz and 3.2GHz.
2. When the VCO clock frequency (FVCO) is below 2.17GHz, VRANGE must be set.
3. The REFDIV, MPY and RATE settings are all associated with a frequency change. The product of all the
frequency changes must match the R value for the selected JMODE.
4. Settings with a higher PLL reference clock (and smaller MPY multiplier) are preferred.
Reference Divider
(REFDIV)
PLL (mul plier)
(MPY)
Receiver
(RATE)
DAC Clock (FCLK)
Reference Clock (FREF)
VCO Clock (FVCO)
Serial bit rate (per lane) (FBIT)
Figure 7-52. Serdes Clock Frequency Generation
www.ti.com
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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