DAC39RF10 datasheet(216/232 Pages) TI2

No. de pieza	DAC39RF10

Descripción Electrónicos	DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface

PDF	232 Pages

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Fabricante Electrónico	TI2 [Texas Instruments]

Página de inicio	https://www.ti.com

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Ground Relief Cut-outs

for Impedance Matching

Figure 9-24. Ground Cut-out Below SMA Connector Center Pin

6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in

the ground plane or ground plane clearances associated with power and signal vias and through-hole

component leads.

7. Provide symmetrically located ground tie stitching vias adjacent to any high-speed signal at an appropriate

spacing as determined by the maximum frequency the trace transports (λ/4). See Figure 9-22 as an

example.

8. When high-speed signals must transition to another layer using vias, transition as far through the board as

possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is

not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place two ground vias (“return

vias”) close to critical high-speed signal trace via when transitioning between layers to provide a nearby

ground return path. See Figure 9-25 and Figure 9-26 as examples.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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DAC39RF10 Datasheet(PDF) 216 Page - Texas Instruments