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CAP3001A Datasheet(PDF) 17 Page - Micronas |
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CAP3001A Datasheet(HTML) 17 Page - Micronas |
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17 / 37 page  CAP 3001 A MICRONAS INTERMETALL 17 2.1.22. Clock Generation The CAP 3001 A processor has an integrated clock os- cillator which is crystal-controlled and oscillates with the frequency fECLK+16.416 MHz. All components of the oscillator are integrated except for the quartz crystal. This is connected to the QX1 and QX2 oscillator pins. The crystal input QX2/ECLK can be used to supply the CAP 3001 A externally with the required clock. In this case no crystal is needed. Following the clock oscillator is a frequency multiplier with a factor of 3. The output of the frequency multiplier delivers the fICLK internal clock frequency, by which the DSP Core is clocked. There is the possibility of pulling the fECLK oscillator fre- quency in a range of 350 ppm, depending on the applica- tion and the used crystal. This makes it possible to syn- chronize the CAP 3001 A to the incoming pilot tone signal in the case of MPX reception. Table 2–1: Oscillator characteristics DCO Content Frequency 011111111B 000000000B 100000000B fECLKmin fECLK fECLKmax DCO Clock Control Register Clock Oscillator Frequency Multiplier Clock Pulse Shaper and Frequency Divider Φ1 Φ2 Φ3 Φ4 9 39 38 62 fICLK CLKOUT fECLK Fig. 2–17: Clock generator connections GNDD 1 nF ECLK 100 nF 39 38 external option |
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