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CAP3001A Datasheet(PDF) 15 Page - Micronas |
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CAP3001A Datasheet(HTML) 15 Page - Micronas |
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15 / 37 page  CAP 3001 A MICRONAS INTERMETALL 15 2.1.20. The IM Bus Interface of the CAP 3001 A MSB LSB shift MSB LSB shift IM Bus Control IMDATA IABF IDBF Data Bus 10 16 IMCLK IMIDENT Fig. 2–14: IM-bus interface The buffer part consists of a unidirectional address buff- er IABF with a word length of 10 bit and the bidirectional data buffer IDBF with a word length of 16 bit. It is only possible to write to the address buffer from the peripher- al equipment. By means of the IM-bus interface it is possible, for exam- ple, to alter the filter coefficients of the CAP 3001 A. For this purpose the microcomputer writes an address and a data word to the appropriate buffers IABF and IDBF. The 10-bit address contains an address part of 8 bits (bit 9 to bit 2), a read/write bit (bit 0) and an additional bit (bit 1) which may be used, for example, for select- ing one of the two address counter banks (Fig. 2–15). Bits 0 and 1 have the following effect: ABNK +0 selects address counter bank 1 ABNK +1 selects address counter bank 2 R/W +0 selects Write, microcomputer wants to write R/W +1 selects Read, microcomputer wants to read MSB R/W ABNK LSB Address Fig. 2–15: Address format The following convention is applicable to the data trans- fer: The last bit written always becomes the MSB of IABF or IDBF. If fewer bits are transferred than the respective buffer size, the unused bits are set to zero in IDBF but remain undefined in IABF. For the output: the first bit out- put is always the LSB of the IDBF. 2.1.21. Description of the IM Bus The IM-bus consists of three lines for the signals Ident (IMIDENT), Clock (IMCLK) and Data (IMDATA). The clock frequency range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the controller to the slave ICs, Data is bidirectional. Bidirectionality is achieved by us- ing open-drain outputs with on-resistances of 150 Ohm maximum. The 2.5 k Ω pull-up resistor common to all out- puts is incorporated in the controller. The timing of a complete IM-bus transaction is shown in Fig. 2–16. In the non-operative state the signals of all three bus lines are High. To start a transaction, the con- troller sets the ID signal to Low level, indicating an ad- dress transmission, sets the CL signal to Low level and switches the first bit on the Data line. Then 10 address bits are transmitted, beginning with the LSB. Data take- over in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave the IM-bus interface switches over to Data read or write, because these func- tions are correlated to the address. In the case of a read operation, a fixed wait period has to be observed. This period is defined by the IM-bus han- dler in the DSP software. For practical reasons this part of the program does not run at the full sampling rate. It is recommended to place the IM-bus handler in a “low speed” time slice in order to save processing power. For a write operation this wait period does not have to be observed, but please note that the maximum rate of IM- bus transmissions is normally limited by the DSP soft- ware. Also controlled by the address the controller now trans- mits sixteen clock pulses, and accordingly two Bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. A bus transaction may be interrupted for up to 10 ms. |
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