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CAP3001A Datasheet(PDF) 14 Page - Micronas |
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CAP3001A Datasheet(HTML) 14 Page - Micronas |
14 / 37 page ![]() CAP 3001 A MICRONAS INTERMETALL 14 SDATA SCLK_IN/OUT WS_IN/OUT 16, 24, 32 x Tbck Tbck 1 Tbck: programmable MSB LSB LSB MSB MSB/LSB first programmable 0, 8, 16 x Tbck: programmable delay polarity programmable Tbck +1/Fbck Fbck +32@Fsaudio or Fbck +48@Fsaudio or Fbck +64@Fsaudio Fig. 2–13: Timing of the signals ERR The modes are: – 16-bit wordframe in this case the programmable delay is set to zero; – 24-bit wordframe in this case the programmable delay is set either to 0 or to 8 Tbck; this allows left or right adjusted handling of the 16 data bits – 32-bit wordframe in this case the programmable delay is set either to 0 or to 16 Tbck; this allows left or right adjusted handling of the 16 data bits. In all modes: MSB or LSB-first can be selected; one bit delay between active slope of WSI/O and first wordframe bit is programmable; the polarity of WSI/O can be programmed ; in the 24 and 32-bit wordframes the open data bit loca- tions are MSB or LSB extended (depends on left or right adjustment). Input format and output format can be programmed sep- arately. The restrictions are: A 24-bit wordframe can only be sent if a 24-bit word- frame is also received. In the analog input mode, the 24-bit wordframe output is not allowed. |
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