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CAP3001A Datasheet(PDF) 31 Page - Micronas |
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CAP3001A Datasheet(HTML) 31 Page - Micronas |
31 / 37 page CAP 3001 A MICRONAS INTERMETALL 31 4. Starting the Processor After power-up, the crystal oscillator has to have been started before the Reset reaches high level. An addition- al wait time of 0.4 ms has to be taken into account be- cause of a DSP-internal self-test algorithm. Then a de- fined start of the system can take place. Fig. 4–1 shows the complete startup sequence of the typical application. The DCO register is loaded with a precisely defined- mean value. 2.4 V 4.75 V VSUPD VSUPA Crystal Oscillator Reset > 0.4 ms > 1 ms Fig. 4–1: Startup sequence 5. Synthesizer With the synthesizer block in the CAP 3001 A, a PLL tun- ing system can be implemented for FM and AM receiv- ers. The signal picked up from the mixing oscillators of the FM and AM tuners can be fed to the synthesizer block by means of highly sensitive input pins. Freely pro- grammable dividers, operating with frequencies up to and over 100 MHz, scale the incoming signals to a refer- ence frequency of 25 kHz. This holds true even in the case of AM, which gives AM tuning a considerable speed improvement over common designs. In order to get a tuning step size of down to 300 Hz, the reference divider is also programmable. Incoming frequencies in the range of 0.5 MHz up to more than 100 MHz can be handled, so that the designer is free to choose either a 10.7 MHz or a 450 to 460 kHz IF frequency for the AM case. The common reference frequency for AM and FM allows the implementation of a common PLL filter for the tuning output. FMOSCIN Programmable Divider (16 bit) Φ Reference Clock 16.416 MHz or external REFCLK Current Source Gain adjust AMOSCIN ) * ) * Filter Filter FMTUNOUT AMTUNOUT Program- mable Divider (10 bit) Fig. 5–1: Synthesizer block diagram FMOSCREF AMOSCREF |
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